1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a static random access memory device comprising a first active region having an annular shape and a second active region bisecting the annulus and a manufacturing method thereof.
2. Description of Related Art
Research into a static random access memory (SRAM) cell consisting of two transmitting transistors, two driving transistors and two resistors has been performed in various fields, including a CMOS SRAM using a silicon-on-insulator (SOI) layer for reducing the power consumption and required area of a memory cell. The CMOS SRAM uses a thin-film transistor (TFT), instead of polysilicon having high resistance, as a resistor, and is thus very useful for reducing standby current.
FIG. 1 is a general circuit diagram of an SRAM cell and shows a full CMOS SRAM using a PMOS TFT as the resistor.
The CMOS SRAM cell comprises an NMOS first transmitting transistor T.sub.1 whose gate is connected to a word-line and whose drain (or source) is connected to a first bit line; an NMOS second transmitting transistor T.sub.2 whose gate is connected to the word-line and whose drain (or source) is connected to a second bit line; an NMOS first driving transistor T.sub.3 whose drain is connected to the source (or drain) of first transmitting transistor T.sub.1, whose source is connected to a first constant power line V.sub.ss (i.e., ground) and whose gate is connected to the source (or drain) of second transmitting transistor T.sub.2 ; an NMOS second driving transistor T.sub.4 whose drain is connected to the source (or drain) of second transmitting transistor T.sub.2, whose source is connected to first constant power line V.sub.ss and whose gate is connected to the source (or drain) of first transmitting transistor T.sub.1 ; a first PMOS TFT T.sub.5 whose drain is connected to the source (or drain) of first driving transistor T.sub.3, whose source is connected to a second constant power line V.sub.cc and whose gate is connected to the gate of first driving transistor T.sub.3 and the source (or drain) of second transmitting transistor T.sub.2 ; and a second PMOS TFT T.sub.6 whose drain is connected to the source (or drain) of second driving transistor T.sub.4, whose source is connected to second constant power line V.sub.cc and whose gate is connected to the gate of second driving transistor T.sub.4 and the source (or drain) of first transmitting transistor T.sub.1.
FIG. 2 is a diagram showing a conventional layout of the SRAM cell, obtained from an article entitled "A Stacked Split Word-line (SSW) Cell for Low Voltage Operation, Large Capacity, High Speed SRAMs" (see: IEDM '93, pp809-812). Here, reference numeral 100 designates a mask pattern defining a semiconductor substrate into active and non-active regions, reference numerals 102 and 104 are mask patterns for forming the gates of first and second driving transistors, reference numerals 106 and 108 are mask patterns for forming the gates of first and second transmitting transistors, reference numeral 110 is a mask pattern for forming a contact hole for connecting first constant power line V.sub.ss to the active region, and reference numeral 112 is a mask pattern for forming first constant power line V.sub.ss.
In FIG. 2, the layout drawn in the same mask is represented as the same kind of lines. For example, mask patterns 102 and 104 represented by a dot/dashed line are the layouts drawn in a first mask, and mask patterns 106 and 108 represented by two dots/dashed line are the layouts drawn in a second mask. Referring to FIG. 2, under the consideration of a general photo etching process in which one mask is used for one etching process, it is known that the gates of first and second transmitting transistors and the gates of first and second driving transistor are formed on different levels.
According to the layout of FIG. 2, mask pattern 110 for forming the contact hole for connecting first constant power line V.sub.ss to the active region is placed between mask patterns 104 for forming the gate of the driving transistor. Also, mask pattern 100 for forming the active region is arranged over the whole cell array, as an annular shape.
FIGS. 3A-3D are cross-sectional diagrams cut along line III--III' of FIG. 2 and FIGS. 4A-4D are cross-sectional diagrams cut along line IV--IV' thereof, for illustrating a conventional SRAM cell manufacturing process.
Referring to FIGS. 3A and 4A, a field oxide layer 12 is formed on the surface of a substrate 10 by an oxidation process adopting mask pattern 100. After a first gate oxide layer 14, a first conductive layer and a first insulating layer are stacked on the whole surface of the resultant structure, a photolithography process using mask patterns 102 and 104 is performed, so that gate (not shown) of first driving transistor T.sub.3 and gate 16 of second driving transistor T.sub.4 are formed. Subsequently, a second insulating layer is deposited on the whole surface and then etched back, so that spacers are formed on the sidewalls of the gates of first and second driving transistors T.sub.3 and T.sub.4. As a result, a first insulating layer 18 for insulating the gates of first and second driving transistors from another conductive layer (not shown) is formed.
Referring to FIGS. 3B and 4B, after sacrificially oxidizing the resultant, a wet etching is performed, so that the surface of the active region damaged by the processes for forming the gates of first and second driving transistors and first insulating layer 18 is cured. After a second gate oxide layer 20 and a second conductive layer are stacked on the whole surface of the resultant structure, a photolithography process is performed using mask patterns 106 and 108, so that gates 22 and 24 of first and second transmitting transistors T.sub.1 and T.sub.2 are formed. Then, impurities are doped on the whole surface of the resultant structure, and the source/drain regions 17, 19, 21 and 23 of each transistor are formed.
Referring to FIGS. 3C and 4C, after a third insulating layer is deposited on the resultant structure on which bulk transistors (that is, first and second transmitting transistors T.sub.1 and T.sub.2 and first and second driving transistors T.sub.3 and T.sub.4) are formed, the resultant structure is etched back, to thereby form spacers 26 on the sidewalls of gates 22 and 24 of the first and second transmitting transistors T.sub.1 and T.sub.2. Then, impurities are doped on the whole surface of the resultant structure, to thereby make the source/drain regions 21 and 23 of the first and second transmitting transistors T.sub.1 and T.sub.2 as a lightly doped drain (LDD) structure.
Referring to FIGS. 3D and 4D, after forming a second insulating layer 32 on the whole surface of the resultant structure, the photolithography process using mask pattern 110 is performed. Thus, the contact holes C for connecting first constant power line V.sub.ss with the source (not shown) of first driving transistor T.sub.3 and with the source 19 of second driving transistor T.sub.4 are formed while being self-aligned to the gates of first and second driving transistors. After depositing a third conductive layer on the whole surface of the resultant structure, the photo etching process using mask pattern 112 is performed, to thereby form first constant power line V.sub.ss 34 which connects to the active region via contact hole C.
According to the conventional layout diagram of the SRAM and the manufacturing method thereof, since the gates of the driving transistor and the transmitting transistor are formed on different conductive layers, the size of the unit cell can be reduced. There are, however, certain problems with the above conventional technique, as follows.
First, the gate oxidation layer is formed twice. That is, since gate oxidation layer 14 of the driving transistor and gate oxidation layer 20 of the transmitting transistor are separately formed, the process is complicated.
Second, since gate oxidation layer 20 of the transmitting transistor is formed after gate 16 of the driving transistor is formed, the quality of gate oxidation layer 20 of the transmitting transistor may be deteriorated due to the damages generated on the substrate surface during the formation of gate 16 of the driving transistor. During the processes shown in FIGS. 3B and 4B, the sacrificial oxidation and wet etching are performed to prevent the quality deterioration of the gate oxidation layer of the transmitting transistor, to thereby cure the damaged portion on which the gate oxidation layer of the transmitting transistor is formed. However, this complicates the process.
Third, the width of spacers A formed on the sidewalls of gate (not shown) of the first driving transistor and gate 16 of second driving transistor is different from that of spacers 26 formed on the sidewalls of gates 22 and 24 of the first and second transmitting transistors. Referring to FIGS. 3A and 4C, the width of spacers A formed on the sidewalls of gate (not shown) of the first driving transistor and gate 16 of second driving transistor is wider than that of spacers 26 formed on the sidewalls of gates 22 and 24 of the first and second transmitting transistors, because spacers 26 are formed through just one depositing/etching process while spacers A are formed through two such processes (i.e., for forming gate (not shown) of the first driving transistor and gate 16 of the second driving transistor and for forming gates 22 and 24 of the first and second transmitting transistors). The change of width of the spacers formed on the sidewalls of the gates directly effects a cell ratio. As described above, if the width of the spacers formed on the sidewalls of gates of the driving transistors is wider than that of the spacers formed on the sidewalls of the gates of the transistors, the cell ratio decreases in accordance with the ratio of the driving transistor's current to the transmitting transistor's current.
Fourth, the area of the contact hole decreases. That is, referring to FIG. 4D, if the distance between gates 16 is defined as a minimum feature size, the width of contact hole C formed therebetween decreases to below the minimum feature size due to the spacers A formed on the sidewalls of the gates during each etching back process, to thereby increase the contact resistance of first constant power line V.sub.ss.